Video services can be provided to subscribers by compressing a video signal using a coding circuit at a transmitting station. The compressed video signal is then transmitted via a telecommunication network such as a packet network to a remotely located subscriber station. At the subscriber station, the video signal is decompressed through use of a decoding circuit to reconstruct the original signal. It is expected that High Definition Television (HDTV) signals will be transmitted to subscribers in this manner.
Typically, a video coding circuit includes a processor for performing an orthogonal transform such as a discrete cosine transfer (DCT) and a quantizer for quantizing the transform coefficients resulting from the orthogonal transform. The coding circuit can code a frame of video using an intra-frame or an inter-frame compression technique. A frame of video to be coded is divided into blocks of pixels which may be 8.times.8 or 16.times.16 blocks. If the frame is coded using an intra-frame compression technique, the orthogonal transform is applied directly to each block of pixels and the resulting transform coefficients are quantized. If the frame of video is coded using an inter-frame technique, on a block-by-block basis, a decision is made to directly transform and quantize the actual block or to transform and quantize a predictive error which is the difference between the actual block and a prediction. Illustratively, the prediction is a motion-compensated prediction based on a previous frame. Some video coding circuits utilize only the intra-frame mode while other video coding circuits code some frames with an intra-frame mode and some frames with an inter-frame mode. In both the intra-frame and inter-frame mode, the quantized transform coefficients are converted by a coder into variable length (VLC) or fixed length (FLC) code words for transmission to a remote location. In some cases, the coder comprises a run-length coder followed by a variable length coder.
In a variety of applications, it is desirable to control the number of code bits generated by the coding circuit for particular frames. For example, if there is congestion in the network, it may be desirable to reduce the number of code bits generated by the coding circuit to reduce the average bandwidth required to transmit the video signal through the network.
In another example, it may be desirable to control the rate at which the coding circuit generates code bits so as to insure that code bits are transmitted from the coding circuit into the network at a smooth rate. It should be noted that for a particular frame, an intra-frame coding mode results in more code bits than an inter-frame coding mode. Furthermore, busy frames and frame portions result in the generation of more code bits than smooth frames and frame portions. Thus, in general, a video coding circuit generates code bits at a variable bit rate.
Some networks can handle the local fluctuations in bit rate produced by the coding circuit and the code bits are transmitted at a variable bit rate directly into the network. For other networks, it is necessary to smooth out the fluctuations in bit rate generated by the coding circuit before the code bits are transmitted into the network. The rate smoothing can be accomplished by use of a rate buffer which interfaces between the coding circuit and the network. Code bits are written into the rate buffer at a variable rate by the coding circuit and transmitted from the rate buffer into the network at a desired constant or approximately constant rate. To carry out this scheme, it is necessary to maintain the fraction of the rate buffer which is occupied within predetermined upper and lower limits. Thus, in a typical scheme, the contents of the rate buffer are fed back to the coding circuit to control the amount of code bits generated by the coding circuit.
The prior art discloses a number of techniques for controlling the rate at which code bits are generated by the coding circuit.
To adjust the rate at which code bits are produced by a coding circuit, the coarseness of the quantizer may be adjusted (see e.g. W. Chen and W. K. Pratt, "Scene Adaptive Coder", IEEE Trans. Commun., Vol. COM-32, pp. 225-232, March 1984 and C. T. Chen et al, U.S. patent application Ser. No. 381,860 filed Jul. 19, 1989 and assigned to the assignee hereof). A coarse quantizer (i.e. a quantizer with a large step size) results in fewer code bits than a fine quantizer (i.e. a quantizer with a small step size). A problem with this approach for controlling the rate at which code bits are generated by a video coding circuit is that unacceptable artifacts may be produced when the quantizer is made very coarse to fit the signal within a specified bandwidth.
If the allowed budget of bits is too tight, another option is to decimate the signal spatially and/or temporally before coding. Typically, the source signal is decimated horizontally and vertically by a factor of two to obtain a quarter-size frame. However, use of a quarter-size frame can result in a coded image which is of poor quality. The drastic reduction in samples which occurs when there is a conversion to a quarter-size frame makes it difficult to achieve a desired amount of code bits while also maintaining a desired level of quality in the coded video signal. The coding algorithm cannot make up for the reduced number of samples in a quarter-size frame through quantization with a fine quantizer having a very small step size. There is a range of rates for which using a fine quantizer does not make up for the loss of quality resulting from use of a quarter-size frame in forming a coded image.
To overcome this problem, the present invention uses a coding circuit and coding method which achieve a more gradual reduction in frame size than the reduction to quarter-size frames utilized in the prior art. Preferably, the present invention utilizes spatial reduction of M/N in each of the horizontal and vertical dimensions for a total frame size reduction of M.sup.2 /N.sup.2, where M and N are integers and where O&lt;M/N&lt;1.
The normal procedure for a conversion by a factor M/N consists of first using interpolation (sampling rate increase) by a factor of M followed by decimation (sampling rate decrease) by a factor of N (see e.g., R. E. Crochiere et al., "Multirate Digital Signal Processing", Prentice Hall, Englewood Cliffs, N.J., 1983) In practice, these interpolation and decimation operations are carried out using periodically shift-varying filters that are derived from interpolation and decimation filters using a polyphase representation. However, such filters are quite complex and are difficult to implement, especially when the flexibility to select among different M/N ratios is desired. One reason for the difficulty in achieving flexibility is that the polyphase periodically shift-varying filters combine both low pass anti-aliasing filtering and interpolation and decimation.
In view of the foregoing, it is an object of the present invention to provide a method and circuit for coding a video image wherein the number of code bits produced can be varied while still maintaining a desired level of coded image quality. More specifically, it is an object of the present invention to provide a video coding circuit and method in which a preprocessing filter stage flexibly achieves a selected frame size reduction in both the horizontal and vertical directions to control the number of code bits generated by a video coding circuit. It is a further object of the present invention to provide a video coding circuit and method which controls the number of code bits by controlling the frame size in combination with controlling the quantizer step size.